1. Field of the Invention
This invention relates to semiconductor process equipment and methods, and more particularly, to Chemical Vapor Deposition (CVD) apparatuses and methods for performing a plurality of in situ processes for forming all or portions of an electronic device.
2. Background of the Invention
Present Chemical Vapor Deposition Equipment consists of multiple chambers, gas inlets, gas outlets, vacuum pumps and transfer load-lock systems for inserting, for example, semiconductor wafers into the chambers. Examples of Chemical Vapor Deposition Equipment are described in U.S. Pat. No. 5,259,918 issued on Nov. 9, 1993, which shows an Ultra High Vacuum Chemical Vapor Deposition (UHV-CVD) reactor with a vacuum loading chamber; and in U.S. Pat. No. 6,013,134 issued on Jan. 11, 2000, which shows a UHV transfer system for transferring wafers between a UHV-CVD reactor and a Low Pressure-Chemical Vapor Deposition (LPCVD) reactor. The entire contents of both of these patents are incorporated herein by reference.
In the growth of Si structures of Si/SiGe heterostructures via UHV-CVD processing according to the prior art, a critical step and requirement before loading wafers into the UHV-CVD equipment is to perform a dip of each Si containing wafer into hydrofluoric (HF) acid to remove the native oxide from the wafer surface and to passivate the Si bonds at the surface with hydrogen. Si containing wafers after being dipped in HF acid are loaded into a vacuum loading apparatus of a CVD reactor and then inserted into the CVD reactor. This particular HF cleaning procedure is a hazardous practice to be performed manually under a chemical hood and moreover, for patterned wafers, often there is residual HF liquid left on the wafer surface which would require removal before continuing to process the wafers. Removing residual liquid HF is an extremely hazardous manual process. Presently, this HF-dip is not an industry acceptable process and weakens the acceptance of the UHV-CVD processing technique for doing low temperature epitaxy in the semiconductor manufacturing industry.
Another key issue related to making high performance Si and/or Si/SiGe Metal Oxide Silicon (MOS) field effect transistor (FET) structures and/or Complementary Metal Oxide Silicon (CMOS) structures is the requirement for a very high quality gate dielectric and a gate electrode stack as described in U.S. Pat. No. 5,534,713 by K. Ismail et al. which issued Jul. 9, 1996, and the entire contents of which are incorporated herein by reference. This patent describes a gate dielectric of an ultra-thin SiO2 layer with a thickness from 1 nm to 5 nm. The gate electrode is a heavily doped polysilicon structure.